1. Field
The exemplary embodiments relate to wireless communications, and more particularly, to a method for effectively designing circuits which form a time division duplex (TDD) transceiver.
2. Description of the Related Art
FIG. 1 illustrates a conventional direct conversion type transceiver device. In general, such a transceiver device comprises a radio frequency (RF) chip 100, which processes RF signals, and a digital baseband chip 190, which processes digital signals in a baseband.
The RF chip 100 comprises a receiver chain 150, which processes received signals, and a transmitter chain 160, which processes signals to be transmitted.
Firstly, in signal processing of the receiver chain 150, a low noise amplifier 151 amplifies the RF signals received through an antenna and minimizes noise in the RF signals.
The amplified signals are frequency down converted into signals in a baseband by a mixer 152 using signals outputted from a phase locked loop (PLL) 170.
The signals in a baseband outputted from the mixer 152 are amplified by a baseband analog (BBA) amplifier 154 via a BBA filter. In general, variable gain amplifiers (VGA) are used as the BBA amplifiers 154 and 162.
Signals processed by the receiver chain 150 in this way are transferred to the digital baseband chip 190. The transferred signals are converted into digital signals by an analog/digital (A/D) converter 110 and are demodulated by a modem 130.
Meanwhile, a procedure for transmitting signals is performed in a reverse order. In other words, bit streams in a baseband are modulated by the modem 130 using phase shift keying (PSK) or quadrature amplitude modulation (QAM) and are then converted into analog signals by a digital/analog (D/A) converter 120.
The converted signals are frequency up converted by a mixer 163 via the BBA filter 161 and the BBA amplifier 162. The signals output from the mixer 163 are amplified by power amplifiers (PA) 164 and then are transmitted through an antenna.
In this way, in a conventional transceiver, the receiver chain 150 and the transmitter chain 160 are integrated on one chip. Unlike in the case of a digital IC, since an RF chip is not easily scaled down despite the development of a semiconductor manufacturing process, a circuit needs to be designed so as to minimize the size of a semiconductor die.
In particular, as a multi-input multi-output (MIMO) technology for transmitting and receiving data using a plurality of antennas has been recently developed, a plurality of receiver chains and transmitter chains are needed in a transceiver having an MIMO function. In this case, the size of a die is very large and thus costs for producing an RF chip increase.
In addition, as chains increase like in an MIMO technology, layout becomes more complicated. As the size of a package increases, a parasitic effect occurs and performance may deteriorate.